1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2008-274253, filed Oct. 24, 2008, the content of which is incorporated herein by reference.
2. Description of the Related Art
Generally, a BGA (Ball Grid Array) semiconductor device, such as a semiconductor device 1 shown in FIG. 20, schematically includes: a wiring substrate 2 having a surface 2a on which multiple connection pads 3 are provided and a rear surface 2b on which multiple lands 4 electrically connected to the connection pads 3 are provided; a semiconductor chip 5 on the surface 2a of the wiring substrate 2; wires 7 electrically connecting multiple electrode pads 6 on the semiconductor chip 5 and the connection pads 3 on the wiring substrate 2; a seal 8 that is made of an insulating resin and covers at least the semiconductor chip 5 and the wires 7; and multiple solder balls 9 that are external terminals on the lands 4.
Generally, the BGA semiconductor device 1 is manufactured by an MAP (Mold Array Process) method for better productivity. Specifically, a wiring motherboard including multiple wiring substrates (element formation units) arranged in a matrix is processed, and is finally diced into multiple pieces of the element formation units to obtain multiple pieces of semiconductor devices.
There has been a problem in that the BGA semiconductor device 1 warps due to the difference in thermal expansion coefficients between the wiring substrate 2 and the seal 8. Particularly, in the MAP method of simultaneously manufacturing multiple semiconductor devices 1, multiple wiring substrates 2 included in a wiring motherboard are collectively covered by a seal, thereby causing more warpage due to the difference in thermal expansion coefficients between the wiring substrate 2 and the seal 8.
To solve the problem, Japanese Unexamined Patent, First Publication Nos. 2001-44229 and 2001-44324 disclose a method of dividing a seal for covering a wiring motherboard into two or more pieces in order to reduce a region to be simultaneously sealed.
However, in the disclosed method, element formation regions become small since a seal for covering the wiring motherboard is divided into two or more pieces, thereby degrading the productivity. Consequently, the number of semiconductor devices obtained from one wiring motherboard is reduced, thereby causing higher costs for manufacturing semiconductor devices.
Recently, demands for more miniaturized and thinned semiconductor devices have been increasing with increasing demands for more miniaturized and thinned mobile devices. Therefore, wiring substrates and semiconductor chips have been becoming thinner and thinner, thereby causing warpage of semiconductor devices obtained by dicing a thin wiring motherboard.
In other words, conventional semiconductor devices obtained by dicing do not warp since each semiconductor piece has rigidity and therefore can withstand stress due to the difference in thermal expansion coefficients. However, thinned semiconductor devices warp since each thinned semiconductor piece has less rigidity and therefore cannot withstand stress due to the difference in thermal expansion coefficients.
Such warpage of semiconductor devices might cause a poor connection such as a poor connection of solder balls when each semiconductor device is mounted on a motherboard. Particularly, a semiconductor device having a PoP (Package on Package) structure in which multiple semiconductor devices are stacked greatly warp.